Enabling Energy Efficient Solutions

Product Overview

I3T50: 0.35 µm Process Technology

Product Description
Providing the density of a 0.35 µm digital process, analog/mixed-signal capability and high voltage, the ON Semiconductor Intelligent Interface Technology I3T50 process is the answer to the need for increased digital content in a mixed-signal and/or high voltage environment. Featuring high voltage devices up to 40 V as well as digital and analog operation at 3.3 V, the I3T50 process family is the first to use deep trenches for isolating high voltage devices.
Features

  • 3 to 5 metal layers
  • Metal to metal (MIM) linear capacitors
  • High-voltage metal capacitors
  • High-resistivity polysilicon resistors
  • Two types of medium-resistivity polysilicon resistors
  • Floating high-voltage NDMOS & PDMOS transistors
  • Floating medium-voltage NDMOS transistors
  • Zener zap diode for OTP
  • Floating high-voltage and low-voltage diodes
  • Polysilicon gate protection diodes
  • Medium-voltage NPN bipolar transistors
  • Deep trench isolation
  • EEPROM capability
  • High temperature capability

Process Characteristics

Operating Voltage 3.3 V
Substrate Material N-epitaxy on P-sub, retrograde wells
Drawn Transistor Length 0.35 µm
Gate Oxide Thickness 7.0 nm
Contact/Via Size 0.4 µm
Contacted Gate Pitch 1.3 µm
Top Metal Thickness 1020 nm
Metal Pitch
   Metal 1 1.0 µm
   Metal 2 1.1 µm
   Top Metal 1.4 µm
Metal Composition AI/Cu
Isolation LOCOS for CMOS, DT for HV
ILD Planarization USG/BPTEOS+CMP
IMD Planarization HDP/PETEOS+CMP

Sample Process Options

  Mask Layers
3 metal, 40 V, MIMC, HIPO, OTP 21
4 metal, 40 V, MIMC, HIPO, OTP 23
5 metal, 40 V, MIMC, HIPO, OTP 25

Device Characteristics

(All Values Typical at 25°C)

Low-Voltage Transistors

NMOS Transistor Typical
Value		 Unit
Vt (10/0.35, linear extrapolated) 0.59 V
Vmax=Vbd 3.6 V
IDS (10/0.35, Vds=Vgs=3.3 V) 530 µA/µm
PMOS Transistor
Vt (10/0.35, linear extrapolated) -0.57 V
Vmax=Vbd -3.6 V
IDS (10/0.35, Vds=Vgs=3.3 V) -250 µA/µm

Diodes (Parameter K_area=6.76 µm²)

Floating High Voltage Diode:FID50 Typical
Value		 Unit
Vbd 51 V
Vak_forw, lk=1µA 0.68 V
Poly Diode for Gate Clamping: POLYD
Vbd 6.8 V
Vbe_forw 0.6 V
Ileak/W @ vrev=5 V 40 nA/µm
Vbd_max 7.5 V

Diodes (Parameter W=2 µm)

Zapping Zener Diode for OTP: Z224 Typical
Value		 Unit
Vz @ 50 µA 2.7 V
Vbd @ 10 mA 4.5 V
Ileak _max @ 1 V 1.7 µA

Capacitors (Parameter @ 25°C)

Metal2/Metal2.5 Capacitor: MIMC Typical
Value		 Unit
C 1.5 fF/µm²
V max 3.6 V
Metal1/Metal3 Plate Capacitor
C 0.1 fF/µm²
V max 50 V
Poly/Metal3 Plate Capacitor
C 0.14 fF/µm²
V max 50 V
Metal1/Metal3 Bar Capacitor
C 0.26 fF/µm²
V max 50 V
Poly/Metal3 Bar Capacitor
C 0.33 fF/µm²
V max 50 V

 

High-Voltage Transistors

Floating NMOS Transistor: VFNDM50 Typical
Value		 Unit
Vt (W=40 µm) 0.77 V
Vdsmax (guaranteed by hot carrier measurements) 40 V
Vgsmax (full lifetime) 3.6 V
Ids (Vds=25 V, Vgs=3.3 V, 4 channels) 220 µA/µm
Ron*Area (20 channels) 52 mΩ*mm²
Floating PDMOS Transistor: LFPDM50
Vt (W=40 µm) -0.57 V
Vdsmax (guaranteed by hot carrier measurements) -40 V
Vgsmax (full lifetime) -3.6 V
Ids (Vds=10 V, Vgs=-3.3 V) -110 µA/µm
Ron*Area 150 mΩ*mm²
Floating Medium Voltage Transistor: LFNDM14
Vt (W=40 µm) 0.59 V
Vdsmax (guaranteed by hot carrier measurements) 14 V
Vgsmax (full lifetime) 3.6 V
Ids (Vds=10 V, Vgs=-3.3 V) 300 µA/µm
Ron*Area 31 mΩ*mm²

Bipolar Transistors (Parameter, E_area=0.16 µm²)

Medium Voltage NPN Typical
Value		 Unit
Hfe @ Ic=50 nA – 0.5 mA (emitter area 0.16 µm²) >100 -
Hfe @ Ic=10 nA – 1.0 mA (emitter area 0.49 µm²) >80 -
Vce max @ Ic=1 µA 11 V
Vce max @ Ic=0 µA 40 V

Resistors (Parameter @ 25°C)

High-Resistance Poly: HIPO Typical
Value		 Unit
Resistance 1000 Ω/square
Unsalicided P+ Poly: PPOLR
Resistance 240 Ω/square
Unsalicided N+ Poly: NPOLR
Resistance 270 Ω/square

 

Libraries

Standard Cell
Ultra High Density Core Cell
pn sum: 2.0
Area of 2-input nand (na21): 38.88 µm²
Gate density (na21 @ 100% utilization): 25.72 k gates/mm²
Scan Flop density (scan flops @100% utilization): 3.215 k ff/mm²
Average power (@ 3.3 V): 0.2929 µW/MHz/gate

Standard I/O
5 V Capable Fat Pad I/O Library (for core limited designs)
191.40 µm min in-line pad pitch
214.60 µm pad height
5 V Capable Tall Pad I/O Library (for pad limited designs)
150.80 µm min in-line pad pitch
417.60 µm pad height
Fat Pad I/O Library (for core limited designs)
174.00 µm min in-line pad pitch
168.20 µm pad height
Tall Pad I/O Library (for pad limited designs)
92.80 µm min in-line pad pitch
330.60 µm pad height

Memory Options

RAM
Synchronous High Speed/High Temp Single Port SRAM
Minimum: 16 words x 2 bits
Maximum: 128 k bits
(ie: 16 k words x 8 bits, 8 k words x 16 bits, …)
Synchronous High Speed/High Temp Dual Port SRAM
Minimum: 16 words x 2 bits
Maximum: 128 k bits
(ie: 16 k words x 8 bits, 8 k words x 16 bits, …)
Low Power Synchronous SRAM
Minimum: 64 words x 4 bits
Maximum: 128 k bits
(ie: 16 k words x 8 bits, 8 k words x 16 bits, …)

ROM
Synchronous High Speed/High Temp Diffusion ROM
Minimum: 256 words x 4 bits
Maximum: 512 k bits
(ie: 64 k words x 8 bits, 32 k words x 16 bits, …)
Low Power Synchronous Via Programmable ROM
Minimum: 256 words x 4 bits
Maximum: 512 k bits
(ie: 64 k words x 8 bits, 32 k words x 16 bits, …)

Non-Volatile Memory
OTP – One Time Programmable
Fuse: Zener Diode optimized for low power zapping
Both Serial and Parallel Output Capability
In field programming available
Vector: Up to 320 bits
EEPROM – No additional masks or processing steps
Differential Bit Cell (Redundancy for High Reliability)
2ms Write/Erase
Array: up to 8 k bits (128x64), Vector: 8 to 64 bits (1x8 to 1x64)
Internal Charge Pump provided
Memory Failure Rate: <10ppm, <1ppm with ECC (128x56)
Automotive qualification AEC-Q100

CAD Tool Compatibility

Digital Design
Synopsys Design Compiler
Cadence Verilog

Analog Design
Cadence DFII (4.4.6)
Spectre

Place and Route
Synopsys Apollo
Cadence Silicon Ensemble

Physical Verification
Mentor Graphics Calibre

For more information please contact your local sales support at www.onsemi.com