Skew Management | MC100EP196

3.3 V ECL Programmable Delay Chip

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概览

The MC100EP196 is a programmable delay chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides programmably variable delay of a differential ECL input signal. It has similar architecture to the EP195 with the added feature of further tuneability in delay using the FTUNE pin. The FTUNE input takes an analog voltage from VCC to VEE to fine tune the output delay from 0 to 60 ps.

  • Maximum Frequency > 1.2 GHz Typical
  • PECL Mode Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.6 V
  • Open Input Default State
  • Safety Clamp on Inputs
  • A Logic High on the ENbar Pin Will Force Q to Logic Low
  • D[0:10] Can Accept Either ECL, LVCMOS, or LVTTL Inputs
  • VBB Output Reference Voltage
  • Pb-Free Packages are Available

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MSL Temp (°C)

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Input Level

Output Level

VCC Typ (V)

fMax Typ (MHz)

td(prog) Min (ns)

td(prog) Max (ns)

td(step) Typ (ps)

tJitter Typ (ps)

tR & tF Max (ps)

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MC100EP196FAG

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CAD Model

Pb

A

H

P

LQFP-32

561AB

2

260

JTRAY

250

Y

ECL

ECL

3.3

1200

8.6

12

11

3

200

Price N/A

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MC100EP196FAR2G

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CAD Model

Pb

A

H

P

LQFP-32

561AB

2

260

REEL

2000

Y

ECL

ECL

3.3

1200

8.6

12

11

3

200

Price N/A

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可靠性数据

Die Related Summary Data

Device: MC100EP196FAG

Equivalent to wafer fab process: MOSAIC

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等效器件小时

平均故障间隔时间/平均无故障时间（按小时计算）

FITS

MOSAIC

0

476668904

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Data is based on the following assumptions.

Note: The temperature and confidence level may be adjusted to your requirements.

Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)

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