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PLL Clock Generators | NB3H5150-01
概览
NB3H5150-01 是一款高性能多速率时钟生长期，可使用 25 MHz 输入参考，基于单个 PLL 同时合成最多四个不同的频率。参考频率可由晶体、LVCMOS/LVTTL、LVPECL、HCSL 或 LVDS 差分信号。REFMODE 引脚选择参考源。三个输出组（CLK1A/CLK1B 至 CLK3A/CLK3B）产生用户可选择的频率： 25 MHz、50 MHz、100 MHz、125 MHz 或 156.25 MHz，并且具有小于 0.3 ps 的超低噪声/抖动性能。第四个输出组 (CLK4A/CLK4B) 可在引脚搭接模式下产生以下整数和 FRAC−N 频率： 25 MHz、33.33 MHz、50 MHz、66.66 MHz、100 MHz、125 MHz、133.33 MHz、156.25 MHz 或 161.1328 MHz。通过 I2C 接口可提供更多可编程频率，且具有不到 1 ps 的抖动性能。在将来的应用说明中会提供详细的注册说明。每个输出块可创建两个单端相内 LVCMOS 输出或一个 LVPECL 输出差分对。在四个输出块中，每个均可通过单独的 VDDO、用于 LVPECL 的 2.5 V/3.3 V、用于 LVCMOS 的 1.8 V/2.5 V/3.3 V 单独供电。串行（I2C 和 SMBUS）接口可编程多种功能，包括每个分频器块的频率和输出电平，并且每个块均可单独启用和禁用。
- Telecom
- Networking
- Ethernet
- SONET
- Flexible Input Reference − 25 MHz Crystal, Oscillator, Single−Ended or Differential
- Four Independent User−Programmable Clock Frequencies from 25 MHz to 250 MHz
- Independently Configurable Outputs
- Up to Eight LVCMOS Single Ended outputs or up to Four Differential LVPECL Outputs or any combination of LVCMOS and LVPECL
- Flexible Input/Core and Output Power Supply Combinations:
- VDD (Core) = 3.3 V ±5% or 2.5 V ±5%
- VDDOn (Outputs) = 3.3 V ±5% or 2.5 V ±5% or 1.8 V ±5% (LVCMOS Only)
- Independent Power Supply per Output Bank
- 300 ps max Output Rise and Fall Times, LVPECL
- 1000 ps max Output Rise and Fall Times, LVCMOS
- 300 fs maximum RMS Phase Jitter (CLK1:4) Integer-N
- 1 ps maximum RMS Phase Jitter (CLK4) Frac-N
- I2C / SMBus Compatible Interface
- −40°C to +85°C Ambient Operating Temperature
- 32−Pin QFN, 5 mm x 5 mm
- Zero ppm Multiplication Error
- Fractional Divide Ratios for Implementing Arbitrary FEC/Inverse−FEC Ratios
- This is a Pb−Free Device
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NB3H5150-01MNTXG
Active
Pb
A
H
P
QFN-32
1
260
REEL
1000
N
TTL
LVPECL
3.3
25
25-250
-
-
0.5
800
300
-40
85
Price N/A
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