PLL Clock Generators | NB3N51054

四路 HCSL/ LVDS 时钟生成器，3.3 V，晶体 - 100 MHz

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概览

NB3N51054 是一款精确、低相位干扰时钟生成器，支持 PCI Express 要求。该器件接受 25 MHz 基础模式并行谐振晶体或 25 MHz 参考时钟信号，以 100 MHz 时钟频率生成四个 HCSL/ LVDS 输出，最大歪曲率 40 ps。通过 I2C 接口，NB3N51054 提供 -0.35% 和 -0.5% 的可选择扩频选项，适用于需要低电磁干扰 (EMI) 以及无扩频选项的优化性能的应用。

  • Networking
  • Consumer
  • Computing and Peripherals
  • Industrial Equipment
  • PCIe Clock Generation Gen 1, Gen 2, Gen 3 and Gen 4

  • Switch and Router
  • Set Top Box, LCD TV
  • Servers, Desktop Computers
  • Automated Test Equipment

  • Spread of −0.35%, −0.5% and No Spread
  • Typical Phase Jitter @ 100 MHz (integrated 12 kHz to 20 MHz): 0.5 ps
  • Typical Cycle-cycle Jitter @ 100 MHz (10k cycles): 20 ps
  • Uses 25 MHz Fundamental Crystal or Reference Clock Input
  • Four Low Skew HCSL or LVDS Outputs
  • I2C Support with Read Back Capability
  • PCIe Gen 1, Gen 2, Gen 3, Gen 4 Jitter Compliant
  • Operating Supply Voltage Range 3.3 V ± 5%
  • Industrial Temperature Range −40°C to +85°C

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Input Level

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VS Typ (V)

fin Typ (MHz)

fout Typ (MHz)

tJitter(Cy-Cy) Typ (ps)

tJitter(Period) Typ (ps)

tJitter(Φ) Typ (ps)

tR & tF Typ (ps)

tR & tF Max (ps)

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TA Max (°C)

Reference Price

NB3N51054DTR2G

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CAD Model

Pb

A

H

P

TSSOP-24

948H-01

1

260

REEL

2500

Y

Crystal

LVDS

3.3

25

100

20

-

0.5

-

-

-40

85

Price N/A

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可靠性数据

Die Related Summary Data

Device: NB3N51054DTR2G

Equivalent to wafer fab process: ONC18

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等效器件小时

平均故障间隔时间/平均无故障时间（按小时计算）

FITS

ONC18

2

6465777234

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Data is based on the following assumptions.

Note: The temperature and confidence level may be adjusted to your requirements.

Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)

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